Patch set 1:Code-Review +1
3 comments:
File src/mainboard/ocp/monolake/Kconfig:
Patch Set #1, Line 17: config INTEGRATED_UART
Do you have serial output in romstage on cold boot ?
File src/mainboard/ocp/monolake/romstage.c:
Patch Set #1, Line 32: 0x0c0ca1);
0x0ca0 is used by the IPMI.
Patch Set #1, Line 33: pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC,
what are the other entries good for ?
Why doesn't it route 6e/6f to LPC ?
Does the SuperIO have a different range assigned ?
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