Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 54: Code-Review+1
(3 comments)
Patchset:
PS54:
Change looks okay to me. It would be good if Subrata/Meera can provide some clarification on the "free running" clock configuration.
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/082cf9db_b1ccebbd
PS47, Line 47: }"
I did that on brya. I leave here to the Intel. […]
SGTM
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/332e0b20_cd0558a9
PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Done
But, it is still not clear.
Configuration 1: For a root port, a clock source would be always on and there is no CLKREQ# associated with it. This is determined by PCIE_RP_CLK_REQ_UNUSED.
Configuration 2: For a root port, a clock source provided by the SoC is not used. This is determined by PCIE_RP_CLK_SRC_UNUSED.
Configuration 3: For a root port, a clock source is assigned, but it is considered as "free running", which I think means clock source would be always on and there is no CLKREQ# associated with it. So how is this different than configuration 1 above?
Subrata/Meera - any inputs on this?
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