Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ......................................................................
Patch Set 2:
(4 comments)
So far, this doesn't seem to take MTRR allocations into account. Please don't submit before this has been analyzed.
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@12 PS2, Line 12: Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for : ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code : exist there except TSEG region. This explains why we can do it. But why should we?
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@12 PS2, Line 12: Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for : ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code : exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) : and other ranges as reserve alone. : Please break lines before 72 chars.
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@17 PS2, Line 17: TEST=Able to build and boot ICL, TGL RVP. Did you compare timestamps yet?
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@19 PS2, Line 19: Without this CL : : : PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 : PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a : : With this CL : : : PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 : PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a : PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b This is already obvious from the code. But how about MTRR allocations? If we run out of variable MTRRs, it might make things worse.