[coreboot-gerrit] Change in coreboot[master]: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/1

diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
index 6cd4c61..67bb9d5 100644
--- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
@@ -214,4 +214,5 @@

# Disable compliance mode
    register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "1"
 end
diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c
index 57b7067..ca18898 100644
--- a/src/mainboard/google/octopus/variants/bobba/variant.c
+++ b/src/mainboard/google/octopus/variants/bobba/variant.c
@@ -8,6 +8,7 @@
 #include <delay.h>
 #include <gpio.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/intel/apollolake/chip.h>

enum {
    SKU_37_DROID = 37, /* LTE */
@@ -74,3 +75,28 @@
    	return;
    }
 }
+
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+
+	if (cfg != NULL) {
+		if (cfg->DisableXhciLfpsPM) {
+			switch (get_board_sku()) {
+			case 33:
+			case 34:
+			case 35:
+			case 36:
+			case 41:
+			case 42:
+			case 43:
+			case 44:
+				cfg->DisableXhciLfpsPM = 0;
+				return;
+			default:
+				return;
+			}
+		}
+	}
+}