Change in coreboot[master]: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/1

diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
index 6cd4c61..67bb9d5 100644
--- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
@@ -214,4 +214,5 @@

# Disable compliance mode
    register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "1"
 end
diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c
index 57b7067..ca18898 100644
--- a/src/mainboard/google/octopus/variants/bobba/variant.c
+++ b/src/mainboard/google/octopus/variants/bobba/variant.c
@@ -8,6 +8,7 @@
 #include <delay.h>
 #include <gpio.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/intel/apollolake/chip.h>

enum {
    SKU_37_DROID = 37, /* LTE */
@@ -74,3 +75,28 @@
    	return;
    }
 }
+
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+
+	if (cfg != NULL) {
+		if (cfg->DisableXhciLfpsPM) {
+			switch (get_board_sku()) {
+			case 33:
+			case 34:
+			case 35:
+			case 36:
+			case 41:
+			case 42:
+			case 43:
+			case 44:
+				cfg->DisableXhciLfpsPM = 0;
+				return;
+			default:
+				return;
+			}
+		}
+	}
+}

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/1/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/bobba/variant.c:

https://review.coreboot.org/c/coreboot/+/40303/1/src/mainboard/google/octopu... 
PS1, Line 82: 	struct soc_intel_apollolake_config *cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
line over 96 characters

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG@9 
PS1, Line 9: Disable XHCI LFPS power management.
Why? Are there problematic devices? Is it at board limitation? (The bug report is not public, and even if it was, a summary of the bug/problem always belongs in the commit message.)

[Sheng-Liang Pan (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#2).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module will lost after idle overnight, with this work around,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/2

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG@9 
PS1, Line 9: Disable XHCI LFPS power management.
> Why? Are there problematic devices? Is it at board limitation? (The bug report is not public, and ev […]

There is a issue about LTE module lost which discussed in b:/146768983, Intel provide the solution can avoid the symptom.

[Sheng-Liang Pan (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#3).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module will lost after idle overnight, with this work around,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/variant.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/3

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: will
is

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: work around
workaround

[Sheng-Liang Pan (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#4).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/variant.c
1 file changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/4

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: work around
> workaround

Thanks

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: will
> is

Thanks

[Sheng-Liang Pan (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#5).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/5

[Sheng-Liang Pan (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#6).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/6

[Marx Wang (Code Review)]

Marx Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 6: Code-Review+1

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG@19 
PS6, Line 19: BRANCH=None
octopus?

[Sheng-Liang Pan (Code Review)]

Hello Marx Wang, build bot (Jenkins), Patrick Georgi, Henry Sun, Marco Chen,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#7).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/7

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 7:

(1 comment)
> Patch Set 6:
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG@19 
PS6, Line 19: BRANCH=None
> octopus?

it should be octopus, Thanks

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/bobba/variant.c:

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
PS7, Line 95: 		case 44:
Bobba variant here supports bobba/sparky/droid/blorb/droid-lte as I know and looks like the disable_xhci_lfps_pm is for droid-lte only.

As a result,
    - it looks like bobba / sparky skus should be listed here as well? otherwise they will be impacted.
    - since droid-lte skus are fewer, could we set default disable_xhci_lfps_pm to 0 then enable it for droid-lte skus here?

[Sheng-Liang Pan (Code Review)]

Hello Marx Wang, build bot (Jenkins), Patrick Georgi, Henry Sun, Marco Chen,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40303

to look at the new patch set (#8).

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/40303/8

[Sheng-Liang Pan (Code Review)]

Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/bobba/variant.c:

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
PS7, Line 95: 		case 44:
> Bobba variant here supports bobba/sparky/droid/blorb/droid-lte as I know and looks like the disable_ […]

agree, it is more clearly to understand this change is specific for LTE sku.
Thanks.

[Marco Chen (Code Review)]

Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 8: Code-Review+2

[Henry Sun (Code Review)]

Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 8: Code-Review+1

Soft ping Patrick, thanks!

[Justin TerAvest (Code Review)]

Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 8: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

Patch Set 8:

(5 comments)

Please remember to mark comments "Done" when they're done. That way the commit is marked unblocked ("All-Comments-Resolved" becomes green)

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/1//COMMIT_MSG@9 
PS1, Line 9: Disable XHCI LFPS power management.
> There is a issue about LTE module lost which discussed in b:/146768983, Intel provide the solution c […]

Done

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: will
> Thanks

Done

https://review.coreboot.org/c/coreboot/+/40303/3//COMMIT_MSG@9 
PS3, Line 9: work around
> Thanks

Done

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40303/6//COMMIT_MSG@19 
PS6, Line 19: BRANCH=None
> it should be octopus, Thanks

Done

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
File src/mainboard/google/octopus/variants/bobba/variant.c:

https://review.coreboot.org/c/coreboot/+/40303/7/src/mainboard/google/octopu... 
PS7, Line 95: 		case 44:
> agree, it is more clearly to understand this change is specific for LTE sku. […]

Done

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40303 )

Change subject: mb/google/octopus/variants/bobba: Disable XHCI LFPS power management
......................................................................

mb/google/octopus/variants/bobba: Disable XHCI LFPS power management

LTE module is lost after idle overnight, with this workaround,
host will not initiate U3 wakeup at the same time with device,
which will avoid the race condition.

Disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303
Tested-by: build bot (Jenkins) 
Reviewed-by: Marco Chen 
Reviewed-by: Henry Sun 
Reviewed-by: Justin TerAvest 
---
M src/mainboard/google/octopus/variants/bobba/overridetree.cb
M src/mainboard/google/octopus/variants/bobba/variant.c
2 files changed, 23 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Justin TerAvest: Looks good to me, approved
  Marco Chen: Looks good to me, approved
  Henry Sun: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
index 6cd4c61..c786a5d 100644
--- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb
@@ -214,4 +214,5 @@

# Disable compliance mode
    register "DisableComplianceMode" = "1"
+	register "disable_xhci_lfps_pm" = "0"
 end
diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c
index 57b7067..089337a 100644
--- a/src/mainboard/google/octopus/variants/bobba/variant.c
+++ b/src/mainboard/google/octopus/variants/bobba/variant.c
@@ -8,6 +8,7 @@
 #include <delay.h>
 #include <gpio.h>
 #include <ec/google/chromeec/ec.h>
+#include <soc/intel/apollolake/chip.h>

enum {
    SKU_37_DROID = 37, /* LTE */
@@ -74,3 +75,24 @@
    	return;
    }
 }
+
+
+void variant_update_devtree(struct device *dev)
+{
+	struct soc_intel_apollolake_config *cfg = NULL;
+
+	cfg = (struct soc_intel_apollolake_config *)dev->chip_info;
+
+	if (cfg != NULL && cfg->disable_xhci_lfps_pm) {
+		switch (google_chromeec_get_board_sku()) {
+		case 37:
+		case 38:
+		case 39:
+		case 40:
+			cfg->disable_xhci_lfps_pm = 1;
+			return;
+		default:
+			return;
+		}
+	}
+}