[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
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Patch Set 2:
> > So far, this doesn't seem to take MTRR allocations into account. Please
> > don't submit before this has been analyzed.
>
> MTRR allocation based on DRAM is taking care the resource input from here. And https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/... will setup DRAM MTRR range. right ?

This has nothing to do with DRAM (I could only make guesses what that
comment tries to tell us, it seems wrong). But you are right that the
call there sets MTRRs up.

Before I put more effort into this, please explain why we should perform
the change.