Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 149:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35523/122/src/mainboard/acer/aspire... File src/mainboard/acer/aspire_vn7_572g/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/35523/122/src/mainboard/acer/aspire... PS122, Line 41: Offset (0xE0),
I'd suggest trying to implement paging
It's trapping to SMM in various places and I couldn't get DCI working (Skylake-U might not support it over USB3-DbC). An SMI handler probably writes to a register or issues a "vendor command," but reverse engineering the right UEFI module could take time.
I may have found it, I'll see how it goes. At some point, maybe it should be done in a follow-up patch.
https://review.coreboot.org/c/coreboot/+/35523/144/src/mainboard/acer/aspire... File src/mainboard/acer/aspire_vn7_572g/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/35523/144/src/mainboard/acer/aspire... PS144, Line 126: Divide
Wait... […]
Right... The "48" below is probably more useful as "0x30," which is a "0" in ASCII.