[coreboot-gerrit] Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/nehalem/Kconfig
M src/northbridge/intel/nehalem/raminit.c
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1

diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 7b56841..bbea9e7 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -22,6 +22,7 @@
    select CACHE_MRC_SETTINGS
    select HAVE_DEBUG_RAM_SETUP
    select C_ENVIRONMENT_BOOTBLOCK
+	select ROMSTAGE_CACHED_CBMEM

if NORTHBRIDGE_INTEL_NEHALEM

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index fe5d5c9..0fb9b8d 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -4756,6 +4756,7 @@

udelay(1000);
    dump_timings(&info);
+	setup_romstage_wb_cbmem_cache();
    cbmem_wasnot_inited = cbmem_recovery(s3resume);

if (!s3resume)