Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37198 )
Change subject: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM ......................................................................
Patch Set 7:
Patch Set 7:
Patch Set 7:
Patch Set 7:
Looks like this improves loading postcar stage with ~1ms. Thanks for testing.
Which timestamps exactly did you compare? It looked like 22ms overall increment to me.
The difference between '3:after ram initialization' and '100:start of postcar' which this change affects.
1ms improvement is just noise here in my opinion, specially when adding new dependency on having AGESA do MTRR setups.
I think we already mostly keep AGESA's MTRR setup be we work around it by using more MTRR's: UC on regular boot to make sure cbmem hits memory before invd in postcar and WB on S3 resume to speed up things.
1ms on ~14ms is indeed just noise here. The advantages are: - No need to punch an UC hole with MTRR's for cbmem to make sure postcar hits memory before invd - postcar is compressed: 16380 vs 12461 (lz4 compressed) - (TODO)Some of the code can be simplified/removed if one can safely assume the presence of clflush.