[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/intel/tglrvp: Add correct memory SPD settings

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has uploaded a new patch set (#3) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/37928 )

Change subject: [WIP]mb/intel/tglrvp: Add correct memory SPD settings
......................................................................

[WIP]mb/intel/tglrvp: Add correct memory SPD settings

Add Tigerlake RVP supported SPDs and update FSP-M UPDs
for MRC boot config.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi 
Change-Id: Id3fd54b051effb9eb2303e0db2217dd28f857368
---
M src/mainboard/intel/tglrvp/romstage_fsp_params.c
A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
M src/mainboard/intel/tglrvp/spd/Makefile.inc
A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
M src/mainboard/intel/tglrvp/spd/spd.h
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
7 files changed, 220 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37928/3