Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
Patch Set 6: Code-Review+1
(7 comments)
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG@14 PS6, Line 14: TEST=emerge-volteer coreboot The most important question is: does it boot? đ
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 49: /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ : PAD_NC(GPP_B19, NONE), : /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ : PAD_NC(GPP_B20, NONE), : /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ : PAD_NC(GPP_B21, NONE), : /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ : PAD_NC(GPP_B22, NONE), These comments would need to be updated to reflect that GSPI1 is not used
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: USER_PRES_FP_ODL Is this comment accurate?
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 156: /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), : /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), I see this has been changed from NF2 to NF1. Is NF1 DMIC_CLK0, though?
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... PS2, Line 8: /* Copied from baseboard and may need to change for the new variant. */
I have tuned GPIO based on Lingcod schematics.
Ack
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/memory.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 5: malefor Oops, this isn't Malefor đ
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 3: device domain 0 on I'd say GSPI1 should be disabled, as the GPIOs for it are not used.