[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gat...

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31534 )

Change subject: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31534/2/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/31534/2/src/soc/intel/cannonlake/fsp_params.... 
PS2, Line 132: params->Enable8254ClockGating = config->clock_gate_8254;
             : 	params->Enable8254ClockGatingOnS3 = config->clock_gate_8254;
Default value for both Enable8254ClockGating and Enable8254ClockGatingOnS3 is 1. With this change, it will be set to clock_gate_8254 which defaults to 0 and I don't see any coreboot mainboard setting it. IIUC, that can result in S0ix failures because of the change in UPD values. Any board that is using CNL should first set clock_gate_8254 before this change goes in.