Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fb63625..843de14 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -46,7 +46,7 @@ register "gen3_dec" = "0x00fc0901"
register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkHdaEnable" = "1"
# PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 4f57b0e..75a399f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -30,6 +30,10 @@ #include <soc/serialio.h> #include <soc/usb.h>
+#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */ @@ -99,20 +103,14 @@ uint8_t SataPortsDevSlp[8];
/* Audio related */ - uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index fc3155f..8b32bc0 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -119,6 +119,19 @@ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)