Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPD's to support Audio enablement.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 29d75f1..a1af2da 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -30,6 +30,10 @@ #include <soc/serialio.h> #include <soc/usb.h>
+#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */ @@ -115,6 +119,16 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8];
+ /* Audio related */ + uint8_t PchHdaDspEnable; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect; + /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to Pcie devices. diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 4c309dd..41d0fd1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <string.h>
/* Debug interface flag */ enum debug_interface_flag { @@ -108,6 +109,19 @@ m_cfg->ECT = 0; /* Early Command Training Enabled */ m_cfg->RefClk = 0; /* Auto Select CLK freq */
+ /* Audio: HDAUDIO_LINK_MODE_I2S_SSP */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; + m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7;
Srinidhi N Kaushik has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Removed reviewer Patrick Rudolph.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 3: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@9 PS3, Line 9: UPD's UPDs
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@13 PS3, Line 13: TEST=Build and boot tigerlake rvp board How did you play and record audio?
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@13 PS3, Line 13: tigerlake Tiger Lake
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@9 PS3, Line 9: UPD's
UPDs
Ack
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@13 PS3, Line 13: tigerlake
Tiger Lake
Ack
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@13 PS3, Line 13: TEST=Build and boot tigerlake rvp board
How did you play and record audio?
I checked with aplay -l from kernel, checked if sound cards are binding. There is a mainboard change with goes with this. I will update that soon
Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement.
BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/4
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 4: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/3//COMMIT_MSG@13 PS3, Line 13: TEST=Build and boot tigerlake rvp board
I checked with aplay -l from kernel, checked if sound cards are binding. […]
Done
Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 32 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/5
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 5: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 5:
can you please fix this build error ?
Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 33 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/6
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 7: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 7: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8: Code-Review-1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect Here, default value of 0 means connected and 1 is disconnected. I am wondering if this config should be named IDispEnabled or something on those lines so that it can be set only by the mainboards that enable IDisp?
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5; Let's not do this here. I think doing the pinmux config in coreboot should be fine.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Here, default value of 0 means connected and 1 is disconnected. […]
Ack
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Let's not do this here. I think doing the pinmux config in coreboot should be fine.
Furquan, i tried the same experiment we did on volteer on tglrvp, I am not able to get the board booting without these configs. I am following up on how it worked on volteer and not on tglrvp. one thing i can think of the change in FSP versions. Will follow up on that. But in the meantime can we have this included here for the bootable recipe ? Without this I am not able get tglrvp booting.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Ack
Can I use IDispDisable ? if we set this to 1 in mainboard then that can translate in fsp_params.c as m_cfg->PchHdaIDispCodecDisconnect = config->IDispDisable; since 1 is disconnect i think it aligns better. let me know what you think
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Can I use IDispDisable ? if we set this to 1 in mainboard then that can translate in fsp_params. […]
Reason I asked to invert the logic is so that the mainboards that don't have to enable it can just skip setting the config in devicetree completely. If IDispDisable is added, then all mainboards that don't use it have to remember to set it to 1 to get it disconnected.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Reason I asked to invert the logic is so that the mainboards that don't have to enable it can just s […]
Sure makes sense, will change it.
Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#9).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 33 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/9
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Sure makes sense, will change it.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Furquan, i tried the same experiment we did on volteer on tglrvp, I am not able to get the board boo […]
What is the issue that you are running into? Can you please raise a bug and start adding all the debug details there? It is difficult to understand what issues Intel is running into without knowing the details.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
What is the issue that you are running into? Can you please raise a bug and start adding all the deb […]
Here is the cros bug which has all the info. Let me know if you need anything else captured there. https://partnerissuetracker.corp.google.com/issues/146390704
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Here is the cros bug which has all the info. Let me know if you need anything else captured there. […]
Added some questions on the bug.
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl... PS8, Line 49: register "PchHdaAudioLinkHdaEnable" = "1" SOC and mainboard changes should go into separate patches.
Aamir Bohra has uploaded a new patch set (#11) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 33 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/11
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl... PS8, Line 49: register "PchHdaAudioLinkHdaEnable" = "1"
SOC and mainboard changes should go into separate patches.
Its for Buildbot, there is dependency for JSL build. We have to keep them together.
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Added some questions on the bug.
attached log as requested in the bug.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
attached log as requested in the bug.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Done
Added a suggestion to the bug.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Added a suggestion to the bug.
I have updated the bug with my comments, can we get this patch merged in the meantime ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
I have updated the bug with my comments, can we get this patch merged in the meantime ?
Did you try the latest diff I provided? I believe with that diff you shouldn't need this UPD setting in coreboot.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Did you try the latest diff I provided? I believe with that diff you shouldn't need this UPD setting […]
We tried a different WA in FSP and verified we dont need to set this in CB. Also the functionality is fine on volteer. I will remove this.
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Raj Astekar, Meera Ravindranath, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#16).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 27 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/16
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
We tried a different WA in FSP and verified we dont need to set this in CB. […]
Done
Wonkyu Kim has uploaded a new patch set (#18) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/18
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 18: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 18: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Done
Is the workaround uploaded somewhere?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@12 PS12, Line 12: none No bug?
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@15 PS12, Line 15: You mentioned that there is a workaround required to make this change work. Can you please upload that workaround and add that change as Cq-Depend here?
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@12 PS12, Line 12: none
No bug?
I dont have a bug for enabling Audio in upstream, do you want me to create one ?
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@15 PS12, Line 15:
You mentioned that there is a workaround required to make this change work. […]
The WA will be in the chrome-internal fsp repo once Nick's uprev patch is merged. Will push it an send you the link once ready.
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Is the workaround uploaded somewhere?
The WA is on top Nick's FSP uprev patch. I will push it once that gets merged.
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Raj Astekar, Meera Ravindranath, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#19).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:149467239 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/19
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@12 PS12, Line 12: none
I dont have a bug for enabling Audio in upstream, do you want me to create one ?
Done
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Raj Astekar, Meera Ravindranath, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#21).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:149467239 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/21
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 21: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 21: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 21: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38147/12//COMMIT_MSG@12 PS12, Line 12: none
Done
I think you can use this: b:147436144
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... PS21, Line 123: HDAUDIO_LINK_MODE_I2S_SSP I am not completely sure what this comment means?
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Raj Astekar, Meera Ravindranath, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#22).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:149467239 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/22
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 22: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 22: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... PS21, Line 123: HDAUDIO_LINK_MODE_I2S_SSP
I am not completely sure what this comment means?
Initially it was just to enable I2S mode.. now that we have SNDW the comment should change. Will update this
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Raj Astekar, Meera Ravindranath, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38147
to look at the new patch set (#23).
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/23
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 23: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 23: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/21/src/soc/intel/tigerlake/ro... PS21, Line 123: HDAUDIO_LINK_MODE_I2S_SSP
Initially it was just to enable I2S mode.. now that we have SNDW the comment should change. […]
Done
Aamir Bohra has uploaded a new patch set (#24) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 33 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/24
Aamir Bohra has uploaded a new patch set (#25) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38147/25
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 25: Code-Review+2
Aamir Bohra has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Removed Code-Review+2 by Aamir Bohra aamir.bohra@intel.com
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 25 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fb63625..843de14 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -46,7 +46,7 @@ register "gen3_dec" = "0x00fc0901"
register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkHdaEnable" = "1"
# PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 4f57b0e..75a399f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -30,6 +30,10 @@ #include <soc/serialio.h> #include <soc/usb.h>
+#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 + struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */ @@ -99,20 +103,14 @@ uint8_t SataPortsDevSlp[8];
/* Audio related */ - uint8_t PchHdaEnable; uint8_t PchHdaDspEnable; - - /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; + uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; + uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; + uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; + uint8_t PchHdaIDispLinkTmode; + uint8_t PchHdaIDispLinkFrequency; + uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index fc3155f..8b32bc0 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -119,6 +119,19 @@ m_cfg->SmbusEnable = config->SmbusEnable; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(m_cfg->PchHdaAudioLinkSspEnable)); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-
Aamir Bohra (Code Review) -
Furquan Shaikh (Code Review)
-
Maulik V Vaghela (Code Review)
-
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Pratikkumar V Prajapati (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Subrata Banik (Code Review)
-
Wonkyu Kim (Code Review)