[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add postcar_frame_add_ramcache() API

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34805 )

Change subject: arch/x86: Add postcar_frame_add_ramcache() API
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Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... 
File src/arch/x86/postcar_loader.c:

https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... 
PS1, Line 135: MTRR_TYPE_WRPROT
> It's not marked as WB yet. It should be the same type as passed in below.

0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB

DCACHE_RAM_BASE is already marked as WB, setting enable_top_of_ram_cache() region again WB, i'm seeing issue. (causes system hang)

https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... 
PS1, Line 138: postcar_frame_add_ramcache
> This name is weird. I think it should reflect that it's top of 32-bit DRAM usage.

name i will fix it