Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42447 )
Change subject: nb/intel/sandybridge/gma.c: Fix lock bits setting ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42447/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42447/1//COMMIT_MSG@10 PS1, Line 10: PM interrupts. I think we should document what locks what first, at least in the commit message.
https://review.coreboot.org/c/coreboot/+/42447/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/gma.c:
https://review.coreboot.org/c/coreboot/+/42447/1/src/northbridge/intel/sandy... PS1, Line 381: 5 The numbering refers to the sequence as it is documented in the SA BIOS Spec (which disagrees with the changes).
https://review.coreboot.org/c/coreboot/+/42447/1/src/northbridge/intel/sandy... PS1, Line 376: gtt_write(0xa004, 0x00000000); Why write 0 and not skip it like the old step 5? What do you know about these registers that you didn't write into the commit message?