3 comments:
Patch Set #1, Line 10: PM interrupts.
I think we should document what locks what first, at least in the
commit message.
File src/northbridge/intel/sandybridge/gma.c:
The numbering refers to the sequence as it is documented in the SA BIOS Spec
(which disagrees with the changes).
Patch Set #1, Line 376: gtt_write(0xa004, 0x00000000);
Why write 0 and not skip it like the old step 5? What do you know about these registers that you didn't write into the commit message?
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