Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 29:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@9 PS27, Line 9: - Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware)
Please wrap lines around at 72 characters
Done
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@16 PS27, Line 16: ITE8728F
nit: IT8728F
Done
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@20 PS27, Line 20: #43133
CB:43133
Done
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 11: register "ide_legacy_combined" = "0x0"
You can drop this
Done
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 13: : /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ : enable_smbus(); : i2c_eeprom_read(0x50, 0, sizeof(spd_buf), spd_buf);
Ack (can be fixed later)
I pushed a commit that moves this to soc code.