[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Fix cpu capabilities detection function

[Xiang Wang (Code Review)]

Hello ron minnich, Philipp Hug, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36944

to look at the new patch set (#2).

Change subject: arch/riscv: Fix cpu capabilities detection function
......................................................................

arch/riscv: Fix cpu capabilities detection function

On some platforms, misa may not be implemented. On such a platform,
reading misa will get zero. At this time, soc is required to
implement a non-standard method to detect the soc function.
Therefore, this modification add interfaces for non-standard
function.

The MXL field of misa is always at the highest two bits, whether it
is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification
fixes the use of a fixed offset to detect the machine length.

Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/cpu.c
M src/arch/riscv/include/arch/cpu.h
3 files changed, 87 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36944/2