Xiang Wang uploaded patch set #2 to this change.

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arch/riscv: Fix cpu capabilities detection function

On some platforms, misa may not be implemented. On such a platform,
reading misa will get zero. At this time, soc is required to
implement a non-standard method to detect the soc function.
Therefore, this modification add interfaces for non-standard
function.

The MXL field of misa is always at the highest two bits, whether it
is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification
fixes the use of a fixed offset to detect the machine length.

Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/cpu.c
M src/arch/riscv/include/arch/cpu.h
3 files changed, 87 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36944/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc
Gerrit-Change-Number: 36944
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <merle@hardenedlinux.org>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Philipp Hug <philipp@hug.cx>
Gerrit-Reviewer: Xiang Wang <merle@hardenedlinux.org>
Gerrit-Reviewer: ron minnich <rminnich@gmail.com>
Gerrit-MessageType: newpatchset