[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
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Patch Set 2:
> Patch Set 2:
>
> Please also note that this effectively reverts your own
> patch CB:21539 and treats things differently than other
> platforms (where DPR is marked cacheable for instance).

Thanks Nico for digging, if you see CB:21539, that CL was meant to add any reserve range into DRAM resource. The assumption there was that Top_of_RAM (0x7700_0000) till TSEG (0x7b00_0000)  is just reserved and TSEG (0x7b00_0000) till BGSM (0x7b80_0000) is cacheable + reserved.

But CB:36216 CL breaks that assumption and making Top_of_RAM till BGSM entire range reserved and cachable.

Current CL is basically to restore the previous assumption where we don't really need to make such bigger memory range cacheable