[coreboot-gerrit] Change in coreboot[master]: nb/intel: Fix 16-bit read/write PCI_COMMAND register

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40835 )

Change subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register
......................................................................

nb/intel: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/northbridge/intel/gm45/iommu.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/x4x/northbridge.c
4 files changed, 6 insertions(+), 19 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 0d106b8..10e0d02 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -36,17 +36,16 @@
    	const pci_devfn_t igd = PCI_DEV(0, 2, 0);

/* setup somewhere */
-		u8 cmd = pci_read_config8(igd, PCI_COMMAND);
-		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-		pci_write_config8(igd, PCI_COMMAND, cmd);
+		pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
    	void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);

/* clear GTT, 2MB is enough (and should be safe) */
    	memset(bar, 0, 2<<20);

/* and now disable again */
+		u16 cmd = pci_read_config8(igd, PCI_COMMAND);
    	cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-		pci_write_config8(igd, PCI_COMMAND, cmd);
+		pci_write_config16(igd, PCI_COMMAND, cmd);
    	pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0);
    }

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index cd64dfe..b3dbe16 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -178,14 +178,10 @@

static void mch_domain_init(struct device *dev)
 {
-	u32 reg32;
-
    struct device *mch = pcidev_on_root(0, 0);

/* Enable SERR */
-	reg32 = pci_read_config32(mch, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(mch, PCI_COMMAND, reg32);
+	pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR);
 }

static const char *northbridge_acpi_name(const struct device *dev)
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 83bc60e..856eab3 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -147,12 +147,8 @@

static void mch_domain_init(struct device *dev)
 {
-	u32 reg32;
-
    /* Enable SERR */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 }

static const char *northbridge_acpi_name(const struct device *dev)
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 45b6ce3..9c32dae 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -131,12 +131,8 @@

static void mch_domain_init(struct device *dev)
 {
-	u32 reg32;
-
    /* Enable SERR */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SERR;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
 }

static const char *northbridge_acpi_name(const struct device *dev)