Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Patch Set 9:
Patch Set 9: Code-Review+1
Patch Set 9: Code-Review+1
Let's see what others have to say.
I'm still not sure *why* we should change this (or why we should keep the current setup).
Angel, the point of making this change would be, we don't need to make those ranges mark cacheable specifically reserve HW range for OS to consume as coreboot has done TSEG/SMM relocation hence benefit has already before, anything we are marking here is for OS usage or telling OS then do we see any need to say those ranges are cacaheable either rather this CL make those HW reserve range just IO_RESERVE.
Those ranges are reserved by the OS. This has nothing to do with marking them cacheable. It's not because you don't need them to be cacheable that it is a good idea to set them up UC. You want to use as little MTRR as possible and marking that region as UC blows up the MTRR solution. It should be marked as reserved_ram instead of mmio_resource, since that is what it really is.