Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34905 )
Change subject: mb/supermicro/x10slm-f: Add new superio support to board's config ......................................................................
Patch Set 9: Code-Review-1
(8 comments)
https://review.coreboot.org/c/coreboot/+/34905/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34905/9//COMMIT_MSG@11 PS9, Line 11: missing that's not why the commit does. It also adds support graphic init and IPMI
https://review.coreboot.org/c/coreboot/+/34905/8/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x10slm-f/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34905/8/src/mainboard/supermicro/x1... PS8, Line 89: register "wait_for_bmc" = "1"
As far as I can see it's not. Did not realize that it is not necessary for the BMC to work. […]
That's unrelated to super I/O.
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x10slm-f/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 88: chip drivers/ipmi needs "select IPMI_KCS"
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 89: device pnp ca2.0 on end how long does it take for the IPMI KCS service to start? On X11SSH it's 35 seconds after coreboot has entered ramstage.
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 94: device pnp 4e.0 off end doesn't exist
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 96: io 0x60 = 0xa00 missing lpc_gen_dec
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 113: io 0x60 = 0x3e8 missing lpc_gen_dec
https://review.coreboot.org/c/coreboot/+/34905/9/src/mainboard/supermicro/x1... PS9, Line 117: io 0x60 = 0x2e8 missing lpc_gen_dec