Attention is currently required from: Paul Menzel, Angel Pons, Iru Cai.
Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46630 )
Change subject: mb/hp: Add EliteBook 820 G2 ......................................................................
Patch Set 9:
(12 comments)
Patchset:
PS9: Rebased on current master.
File Documentation/mainboard/hp/elitebook_820_g2.md:
https://review.coreboot.org/c/coreboot/+/46630/comment/086226ac_de945720 PS8, Line 28: ## Programming
Isn't most of this section similar to that of another laptop with Sure Start?
Yes, most of the following is copied from folio_9480m.
https://review.coreboot.org/c/coreboot/+/46630/comment/15bda94a_df504004 PS8, Line 115: (needs a modified refcode)
Is this modification documented anywhere?
No.
https://review.coreboot.org/c/coreboot/+/46630/comment/c35a6767_ac22276d PS8, Line 119: - DisplayPort : - VGA
How about using a single entry for all video outputs? […]
Done
File src/mainboard/hp/elitebook_820_g2/Kconfig:
https://review.coreboot.org/c/coreboot/+/46630/comment/038736fc_34467e63 PS8, Line 24: config VGA_BIOS_FILE : string : default "pci8086,1616.rom"
Please remove this. The file doesn't exist in the coreboot tree.
Done
File src/mainboard/hp/elitebook_820_g2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46630/comment/ddb01bef_d4fbc29b PS8, Line 14: 0x0
nit: 0
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/2725bddf_1720c214 PS8, Line 20: 0x0
nit: 0
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/478d05ef_f234cf91 PS8, Line 34: register "pcie_port_coalesce" = "1"
Is this needed? 1c. […]
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/01ff7ae9_207a0653 PS8, Line 35: register "pcie_port_force_aspm" = "0" : register "sata_devslp_disable" = "0" : register "sata_devslp_mux" = "0"
devicetree settings default to zero already, I'd omit these.
Done
https://review.coreboot.org/c/coreboot/+/46630/comment/62d8f9a6_79b8b4d3 PS8, Line 70: SlotDataBusWidth2X
out of curiosity, how did you verify this?
`lspci -vvv` shows "LnkCap: Port #6, ... Width x2".
https://review.coreboot.org/c/coreboot/+/46630/comment/6d0084ac_c1443fad PS8, Line 73: device pci 1e.0 off end # PCI bridge
Doesn't exist since Lynx Point, please remove
Done
File src/mainboard/hp/elitebook_820_g2/pei_data.c:
https://review.coreboot.org/c/coreboot/+/46630/comment/755eb5ab_9c5d5bcb PS8, Line 22: USB_PORT_BACK_PANEL);
Put these on the previous line?
Done