Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(6 comments)
Patchset:
PS15:
yes, because there is no chip in between, the registers still go with the SoC chip
Yes!
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/e44787ec_e7b2a81c PS15, Line 32: [PchSerialIoIndexGSPI0] = 0, Don't really need to set this as GSP0 is disabled. Same for CS state below.
https://review.coreboot.org/c/coreboot/+/49007/comment/84a6a313_3d697353 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1, Do we need to initialize GSPI for FPMCU? Wouldn't this be done by the OS?
https://review.coreboot.org/c/coreboot/+/49007/comment/7090cc4a_6f3c2bae PS15, Line 105: #USB3-1 Type A This comment doesn't really look right. Why does a PCIE RP device say USB3? Same for RP4 below.
https://review.coreboot.org/c/coreboot/+/49007/comment/04a2aef0_776fb706 PS15, Line 110: one additional tab here and on next line.
https://review.coreboot.org/c/coreboot/+/49007/comment/3a735977_fa08561e PS15, Line 134: PCIE_RP_LTR Why is LTR not enabled for WLAN and WWAN ports? Also, what about AER?