EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
PS14:
I think it would be good to push a separate change for brya since it is adding new code that wasn't […]
This change will remove, I used for verify buildbot:)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... PS14, Line 6:
nit: one space should be sufficient. same for clk_req below.
Ack
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 160: /* PCIe RP L1 substate */ : enum L1_substates_control { : L1_SS_FSP_DEFAULT, : L1_SS_DISABLED, : L1_SS_L1_1, : L1_SS_L1_2, : } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
This should be moved into the above structure.
okay.