3 comments:
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
I think it would be good to push a separate change for brya since it is adding new code that wasn't […]
This change will remove, I used for verify buildbot:)
nit: one space should be sufficient. same for clk_req below.
Ack
File src/soc/intel/alderlake/chip.h:
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
This should be moved into the above structure.
okay.
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