Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
I'm still convinced that this configures the PCH. 24 entries for 24 […]
I'm not sure, but fsp has the PegPhysicalSlotNumber[3] option for each PEG port. https://github.com/IntelFsp/FSP/blob/c0ec3d793facec1930b0ca227dbfe7943e1cad7...
Maybe this option overrides the PEG port number. By default, it has a value of 0. Maybe this means that PEG0 is used as PCH_PCIe[0] in "soc".
+ And I added a comment to this code.