Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45325 )
Change subject: nb/intel/ironlake: Reserve gap betwen TSEG and BGSM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... File src/northbridge/intel/ironlake/northbridge.c:
https://review.coreboot.org/c/coreboot/+/45325/2/src/northbridge/intel/ironl... PS2, Line 137: it uncacheable, though, for easier MTRR allocation. */
What bugs me is that this only seems cause problems now. […]
Another thing that would work is to mention in the commit message that this gap is extraneous, and shouldn't exist. This would at least suggest that raminit.c might have a bug.