1 comment:
File src/northbridge/intel/ironlake/northbridge.c:
Patch Set #2, Line 137: it uncacheable, though, for easier MTRR allocation. */
What bugs me is that this only seems cause problems now. […]
Another thing that would work is to mention in the commit message that this gap is extraneous, and shouldn't exist. This would at least suggest that raminit.c might have a bug.
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