Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(3 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/05d0c9f4_918bf787 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Do we need to initialize GSPI for FPMCU? Wouldn't this be done by the OS?
Not sure here.
https://review.coreboot.org/c/coreboot/+/49007/comment/59f82fdd_d50a0027 PS15, Line 105: #USB3-1 Type A
This comment doesn't really look right. Why does a PCIE RP device say USB3? Same for RP4 below.
Do we need to enable RP port if this is combo PCIE and USB?
https://review.coreboot.org/c/coreboot/+/49007/comment/5b0c1c5d_b222bb1c PS15, Line 134: PCIE_RP_LTR
Why is LTR not enabled for WLAN and WWAN ports? Also, what about AER?
Previous project not enabled for it. LTR may cause device lose when suspend/resume. Do we need AER, I think it okay to have it?