Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(7 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/76402d33_5948e029 PS15, Line 32: [PchSerialIoIndexGSPI0] = 0,
Don't really need to set this as GSP0 is disabled. Same for CS state below.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/8f395ba6_b49ffa09 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Not sure here.
volteer enable this so keep this. We can remove this after?
https://review.coreboot.org/c/coreboot/+/49007/comment/22769976_52c7be8e PS15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/fc73b5cf_ab28ee33 PS15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/50e11e2e_6c8efa05 PS15, Line 110:
one additional tab here and on next line.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/460b240f_fa705f8d PS15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/fd5b5be3_451ca99e PS15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done