[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

[Raul Rangel (Code Review)]

Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48309

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel 
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
M src/soc/amd/picasso/include/soc/platform_descriptors.h
3 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48309/2