Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39412 )
Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39412/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39412/1//COMMIT_MSG@9 PS1, Line 9: as the values are different : in ES1(L1.1: 2) and ES2(MAX: 0 - FSP default or 4) What does this mean?
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/chi... PS1, Line 126: 4:Max Why are both 0 and 4 max? and what do they refer to?
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/fsp... PS1, Line 117: for Can memcpy be used?
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/fsp... PS1, Line 118: config->PcieRpL1Substates[i] Why is this check required?
https://review.coreboot.org/c/coreboot/+/39412/1/src/soc/intel/tigerlake/fsp... PS1, Line 119: - 1 Why -1?