[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure L1Substates for PCH Root ports

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39412 )

Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports
......................................................................

soc/intel/tigerlake: Configure L1Substates for PCH Root ports

Set value for PcieRpL1Substates as the values are different
in ES1(L1.1: 2) and ES2(MAX: 0 - FSP default or 4)

BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values

Signed-off-by: Wonkyu Kim 
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39412/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index a6bcf08..6a0d290 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -122,6 +122,11 @@
     * clksrc. */
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];

+	/* PCIe RP L1 substate
+	 * 0: FSP default(Max), 1: Disable, 2: L1.1 3: L1.2 4:Max
+	 */
+	uint8_t PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+
    /* SMBus */
    uint8_t SmbusEnable;

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 0dae0fe..f53517d 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -113,6 +113,12 @@
    	}
    }

+	/* RP Configs */
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+		if (config->PcieRpL1Substates[i])
+			params->PcieRpL1Substates[i] = config->PcieRpL1Substates[i] - 1;
+	}
+
    /* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
    if (dev) {