Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL
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Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl...
File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38147/8/src/mainboard/intel/jasperl...
PS8, Line 49: register "PchHdaAudioLinkHdaEnable" = "1"
SOC and mainboard changes should go into separate patches.
Its for Buildbot, there is dependency for JSL build. We have to keep them together.
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom...
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom...
PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6;
: m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2;
: m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7;
: m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4;
: m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3;
: m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Added some questions on the bug.
attached log as requested in the bug.
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Gerrit-Project: coreboot
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