Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 9: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG@14 PS6, Line 14: TEST=emerge-volteer coreboot
The most important question is: does it boot? 😄
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: USER_PRES_FP_ODL
No, the correct is USER_PRES_FP_ODL
Ack
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 156: /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), : /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
Sorry, it is NF2, not NF1.
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 3: device domain 0 on
GSPI1 has been disabled, like gpio. […]
Ack
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 23: register "SerialIoI2cMode" = "{ Nit: I think this has to define all SerialIO devices. It's an array, so uninitialized elements will be zero