Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32334 )
Change subject: Documentation: Explain DDR3 read training ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... File Documentation/getting_started/ram_initialization/ddr3_flyby.md:
https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 9: lower this should be higher and not lower
https://review.coreboot.org/c/coreboot/+/32334/4/Documentation/getting_start... File Documentation/getting_started/ram_initialization/readtraining.md:
https://review.coreboot.org/c/coreboot/+/32334/4/Documentation/getting_start... PS4, Line 45: The MCH must delay the signals to synchronize them again. this is a bit unspecific. It's mostly about the timing of the DQS pairs and their corresponding DQ byte lanes.