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2 comments:

• File Documentation/getting_started/ram_initialization/ddr3_flyby.md:

  • Patch Set #1, Line 9: lower

    this should be higher and not lower

• File Documentation/getting_started/ram_initialization/readtraining.md:

  • Patch Set #4, Line 45: The MCH must delay the signals to synchronize them again.

    this is a bit unspecific. It's mostly about the timing of the DQS pairs and their corresponding DQ byte lanes.

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