[coreboot-gerrit] Change in coreboot[master]: [NOTFORMERGE] force DDR3-2133 speeds

[Angel Pons (Code Review)]

Hello  Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48417

to review the following change.

Change subject: [NOTFORMERGE] force DDR3-2133 speeds
......................................................................

[NOTFORMERGE] force DDR3-2133 speeds

Change-Id: Ie4a057c736f85e246f00f10e9a07368a92ecd859
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_native.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48417/1

diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 3613c05..49b17bf 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -294,7 +294,7 @@
    }

if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
-		return TCK_1333MHZ;
+		return TCK_1066MHZ;

rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);

@@ -348,6 +348,9 @@

ctrl->tCK = get_mem_min_tck();

+	ctrl->cas_supported |= 1 << (14 - 4);
+	ctrl->cas_supported |= 1 << (13 - 4);
+
    /* Find CAS latency */
    while (1) {
    	/*
@@ -379,6 +382,9 @@
    printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
    printk(BIOS_DEBUG, "Selected CAS latency   : %uT\n", val);
    ctrl->CAS = val;
+
+	if (NS2MHZ_DIV256 / ctrl->tCK == 800)
+		die("rip");
 }

static void dram_timing(ramctr_timing *ctrl)