Angel Pons would like Felix Singer, Nico Huber, Arthur Heymans and Patrick Rudolph to review this change.

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[NOTFORMERGE] force DDR3-2133 speeds

Change-Id: Ie4a057c736f85e246f00f10e9a07368a92ecd859
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/northbridge/intel/sandybridge/raminit_native.c
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48417/1

diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 3613c05..49b17bf 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -294,7 +294,7 @@
 	}
 
 	if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
-		return TCK_1333MHZ;
+		return TCK_1066MHZ;
 
 	rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID);
 
@@ -348,6 +348,9 @@
 
 	ctrl->tCK = get_mem_min_tck();
 
+	ctrl->cas_supported |= 1 << (14 - 4);
+	ctrl->cas_supported |= 1 << (13 - 4);
+
 	/* Find CAS latency */
 	while (1) {
 		/*
@@ -379,6 +382,9 @@
 	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
 	printk(BIOS_DEBUG, "Selected CAS latency   : %uT\n", val);
 	ctrl->CAS = val;
+
+	if (NS2MHZ_DIV256 / ctrl->tCK == 800)
+		die("rip");
 }
 
 static void dram_timing(ramctr_timing *ctrl)

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