[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37200

to look at the new patch set (#15).

Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
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nb/intel/sandybridge: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/model_206ax/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
4 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/15