[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit

[Michael Niewöhner (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 )

Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
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Patch Set 13:

(1 comment)

Patchset:

PS1:
> All datasheets I looked at say LPC BIOS_CNTL is 8 bits, and

eSPI and SPI BIOS_CNTL is 32 bits. I've never seen 16 bits
so far. It might not matter, though, if the LPC register
doesn't mind bigger reads/writes.

Intel......... eSPI and LPC/SPI are both 32 bits, too. Intel just didn't mention that in the datasheet. Source: refcode and Intel doc#545845.

AFAICS the fast_spi code does get used by eSPI as well bc the spi part of eSPI is compatible and since the BIOS_CONTROL register and the status bit have the same offset, it will get cleared on eSPI, too.

There are google boards with kbl, cnl and others, that could be tested. @Tim @Matt