Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common: Make top_of_ram till BGSM region mmio_resource ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@12 PS2, Line 12: Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for : ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code : exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) : and other ranges as reserve alone. :
Please break lines before 72 chars.
Done
https://review.coreboot.org/c/coreboot/+/44014/2//COMMIT_MSG@19 PS2, Line 19: Without this CL : : : PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 : PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a : : With this CL : : : PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 : PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a : PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b
we don't ideally as index count is still meeting this requirement https://github. […]
Done
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@10 PS3, Line 10: that one can perform SMRAM relocation faster.
yes, it just to only make TSEG range notthe entire stolen range cacheable, i will update the commit […]
Done
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@15 PS3, Line 15: range as cacheable (+ reserved) and other ranges as reserve alone.
Do you mean to remove TSEG region reservation like below ? I could see if we are not marking this TS […]
@Aaron, i guess you meant this https://review.coreboot.org/c/coreboot/+/44014/5/src/soc/intel/common/block/... this looks good now. thanks
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@58 PS3, Line 58: MTRR: WB selected as default type.
I see. If WRCOMB type is removed, it means we've ran out of variabke MTRRs, which is not good. […]
No change in MTRR layout hence we are good.