[coreboot-gerrit] Change in coreboot[master]: cpu/x86/lapic: Only deliver ExtINT to BSP

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Nico Huber, Paul Menzel, Felix Held.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42434 )

Change subject: cpu/x86/lapic: Only deliver ExtINT to BSP
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Patch Set 11:

(5 comments)

File src/cpu/x86/lapic/lapic.c:

https://review.coreboot.org/c/coreboot/+/42434/comment/83a0fe67_d42528f6 
PS5, Line 9: lvt0_mask
> It's the same for LVT1, should we use it there too?

Done

https://review.coreboot.org/c/coreboot/+/42434/comment/2d489455_9e781fb6 
PS5, Line 13: 	uint32_t lvt0_val = LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING;
> Maybe comment that this is the mask and value (well minus EXTINT but see below) used by […]

Ack

https://review.coreboot.org/c/coreboot/+/42434/comment/8b1e9b43_ea9293bb 
PS5, Line 29: 		| LAPIC_SPIV_ENABLE);
> Sets spurious interrupt to vector 0? And LVT0 for AP used vector 0 too? […]

Ack

https://review.coreboot.org/c/coreboot/+/42434/comment/b0f33051_6e4fbacb 
PS5, Line 34: 		lvt0_val |= LAPIC_DELIVERY_MODE_FIXED | LAPIC_LVT_MASKED;
> 10.5.2 Valid Interrupt Vectors […]

Ack

https://review.coreboot.org/c/coreboot/+/42434/comment/073601d5_35b02060 
PS5, Line 45: 		);
> The spec (B.1) says […]

I cannot figure out what "this one" here referred to.