[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Add PLL and clock init support

[Weiyi Lu (Code Review)]

Weiyi Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43958 )

Change subject: soc/mediatek/mt8192: Add PLL and clock init support
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Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll... 
File src/soc/mediatek/mt8192/pll.c:

https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll... 
PS1, Line 114: 	MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
> BTW, given most calls are MUX_UPD and only very few are MUX, I think one possible change is to drop  […]

Done, but reserve the MUX marco.
It will be MUX_UPD(XXXX, clk_cfg_0, 0, 3, &mtk_topckgen->clk_cfg_update, 0) if you would like to use MUX_UPD only

https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll... 
PS1, Line 457: 	setbits32(&mtk_topckgen->clk_scp_cfg_0 , 0x3ff);
> Please fix this

Done