2 comments:
File src/soc/mediatek/mt8192/pll.c:
Patch Set #1, Line 114: MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
BTW, given most calls are MUX_UPD and only very few are MUX, I think one possible change is to drop […]
Done, but reserve the MUX marco.
It will be MUX_UPD(XXXX, clk_cfg_0, 0, 3, &mtk_topckgen->clk_cfg_update, 0) if you would like to use MUX_UPD only
Patch Set #1, Line 457: setbits32(&mtk_topckgen->clk_scp_cfg_0 , 0x3ff);
Please fix this
Done
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