Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Angel Pons, Aamir Bohra, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44014
to look at the new patch set (#4).
Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ......................................................................
src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster.
Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone.
TEST=Able to build and boot ICL, TGL RVP.
Without this CL :
PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a
MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007b800000 size 0x7b740000 type 6 0x000000007b800000 - 0x0000000080000000 size 0x04800000 type 0 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
MTRR: WB selected as default type. MTRR: 0 base 0x000000007b800000 mask 0x00003fffff800000 type 0 MTRR: 1 base 0x000000007c000000 mask 0x00003ffffc000000 type 0 MTRR: 2 base 0x0000000080000000 mask 0x00003ffff0000000 type 1 MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 0 MTRR: 4 base 0x00000000a0000000 mask 0x00003fffe0000000 type 0 MTRR: 5 base 0x00000000c0000000 mask 0x00003fffc0000000 type 0
With this CL :
PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b
MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6 0x0000000077000000 - 0x000000007b000000 size 0x04000000 type 0 0x000000007b000000 - 0x000000007b800000 size 0x00800000 type 6 0x000000007b800000 - 0x0000000080000000 size 0x04800000 type 0 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
MTRR: WB selected as default type. MTRR: 0 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 1 base 0x0000000078000000 mask 0x00003ffffe000000 type 0 MTRR: 2 base 0x000000007a000000 mask 0x00003fffff000000 type 0 MTRR: 3 base 0x000000007b800000 mask 0x00003fffff800000 type 0 MTRR: 4 base 0x000000007c000000 mask 0x00003ffffc000000 type 0 MTRR: 5 base 0x0000000080000000 mask 0x00003fff80000000 type 0
Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/4