Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44699 )
Change subject: soc/mediatek/mt8192: Add dram control register define and bits define ......................................................................
Patch Set 41:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44699/41//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44699/41//COMMIT_MSG@7 PS41, Line 7: Add dram control register define and bits define Define DRAM registers and APIs
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... File src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h:
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... PS41, Line 111: DutyScan_K_DQ Uppercase for enums
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... PS41, Line 160: /* frequency set point: : * 0 means lower,un-terminated freq; : * 1 means higher,terminated freq : */ Format:
/* * frequency set point: * 0 means lower, un-terminated freq; * 1 means higher, terminated freq */
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... PS41, Line 276: u8 dqs_final_delay[2][2] Either
u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]
or
u8 *dqs_final_delay
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... PS41, Line 284: calType lowercase
https://review.coreboot.org/c/coreboot/+/44699/41/src/soc/mediatek/mt8192/in... PS41, Line 285: u1VrefScanEnable lowercase